LVDS / 135 MHz / 3 x 10 bits / compatible avec THC63LVD103 / LQFP-64
The eP103 LVDS transmitter supports transmission between the host and the flat panel display up to SXGA+ resolutions. The transmitter converts 3×10 bits of Low Voltage TTL data and 3 control bits into 4 LVDS (Low Voltage Differential Signal) data streams. At a maximum input clock rate of 135MHz, each LVDS differential data pair speed is 945Mbps, providing a total throughput of 3.78Gbps. The transmitter can be configured to input clock rising edge or falling edge strobe through an external pin.
The eP103 LVDS transmitter supports transmission between the host and the flat panel display up to SXGA+ resolutions. The transmitter converts 3×10 bits of Low Voltage TTL data and 3 control bits into 4 LVDS (Low Voltage Differential Signal) data streams. At a maximum input clock rate of 135MHz, each LVDS differential data pair speed is 945Mbps, providing a total throughput of 3.78Gbps. The transmitter can be configured to input clock rising edge or falling edge strobe through an external pin.
