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Réf. :

eP196e

Marque :

5.4G 4-Lane DP/eDP 1.2 Emetteur w/ 8-Lane cLVDS Sorties

eP196e is a 5.4G 4-lane DP/eDP transmitter with 8-lane cLVDS input. cLVDS is a super high speed LVDS technology developed by explore. The chip converts video input data from 1 to 8 lanes cLVDS RX into DP/eDP differential signals.
eP196e is integrated with an on-chip eFlash MCU with pre-programmed firmware driver for cLVDS and DP/eDP control. Software development effort can be greatly reduced.

 

Features


•Compliant with VeSA DP/eDP Standard V1.2a
•Support DP/eDP Link Clock Frequency up to 540 MHz
•Support Video Pixel Clock Frequency up to 600 MHz
•Support cLVDS Link Clock Frequency up to 375 MHz
•Support 1-lane, 2-lane, 4-land and 8-lane operation in cLVDS RX
•Support 3-byte, 4-byte, and 5-byte Data Packing mode in cLVDS RX
•Support 1-lane, 2-lane or 4-lane operation in DP/eDP TX
•Support 6-bit, 18-bit, 10-bit and 12-bit Deep Color modes
•Supports On-chip Test Pattern Generation (TPG) for production convenience.
•Support MCCS over DP/eDP AUX channel.
•On-chip eFlash MCU with pre-programmed firmware driver for cLVDS and DP/eDP control
•Supports Power Down Mode
•3.3V and 1.2V power required
•100-Pin LQFP ePAD

 

Block Diagram

Les caractéristique techniques
Type
Nbr channels
Supply Voltage
Low Noise
Channels number
Type
Video Interfaces
SDI interfaces
Vidéo interface
DP/EDP
Vidéo SFP modules
Type
Nombre de cellule
Overcharge Detection Voltage
Overdischarge Detection Voltage
Type
Iout
Vout
Input voltage
Famille
Type
Tolérance fréquence
Dimensions
Voir la description complète

eP196e is a 5.4G 4-lane DP/eDP transmitter with 8-lane cLVDS input. cLVDS is a super high speed LVDS technology developed by explore. The chip converts video input data from 1 to 8 lanes cLVDS RX into DP/eDP differential signals.
eP196e is integrated with an on-chip eFlash MCU with pre-programmed firmware driver for cLVDS and DP/eDP control. Software development effort can be greatly reduced.

 

Features


•Compliant with VeSA DP/eDP Standard V1.2a
•Support DP/eDP Link Clock Frequency up to 540 MHz
•Support Video Pixel Clock Frequency up to 600 MHz
•Support cLVDS Link Clock Frequency up to 375 MHz
•Support 1-lane, 2-lane, 4-land and 8-lane operation in cLVDS RX
•Support 3-byte, 4-byte, and 5-byte Data Packing mode in cLVDS RX
•Support 1-lane, 2-lane or 4-lane operation in DP/eDP TX
•Support 6-bit, 18-bit, 10-bit and 12-bit Deep Color modes
•Supports On-chip Test Pattern Generation (TPG) for production convenience.
•Support MCCS over DP/eDP AUX channel.
•On-chip eFlash MCU with pre-programmed firmware driver for cLVDS and DP/eDP control
•Supports Power Down Mode
•3.3V and 1.2V power required
•100-Pin LQFP ePAD

 

Block Diagram

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